The present invention relates generally to a semiconductor device. More specifically, the invention relates to an improvement for a voltage control circuit device for a well region on a semiconductor substrate during erasure of information in a flash memory capable of electrically writing and erasing information.
An electrically writable and erasable flash memory has been disclosed in "An 80-ns 1-Mb Flash Memory With One-Chip Erase/Erase-Verify Controller", IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 25, No. 5, October, 1990, pp 1147.about.1151, for example. When the flash memory is fabricated into an integrated circuit together with peripheral circuits, it is typically formed into the following construction.
An N-type well region is formed on the surface of a P-type silicon substrate. A P-type well region is formed within the N-type well region. N-type doped regions serving as a drain and a source of a memory element is formed within the P-type well region. On the P-type well region between the drain and source, a floating gate and a control gate are formed.
When the information in the memory element is to be erased, a high voltage is charged to the N-type well region and the P-type well region. At this time, if there is a difference in resistivities, junction capacitances or so forth between the N-type well region and the P-type well region, it is possible to establish a forward bias at PN junction between the well regions, in the transition of the voltage variation from the grounding voltage to the high voltage of the P-type and N-type well regions. Then, holes are injected from the P-type well region to the P-type silicon substrate via the N-type well region. This is a defect because it leads to an unnecessary increase in power consumption. Also, it is possible to cause latching up of a circuit formed by other complementary type MOS transistor by the hole.
Therefore, it is an object of the present invention to provide a semiconductor device which can prevent a temporary forward bias from occurring between the well regions, upon charging a high voltage to the P-type well region and the N-type well region.
Another object of the present invention is to provide a semiconductor device which can certainly maintain a reverse bias between the well regions upon erasure of information in the flash memory and thus will never affect, such as latching up or so forth, for other circuit.